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16-bit, single channel digital-to-analog converter with internal reference and parallel interface dac7741 sbas248b ?december 2001 ?revised august 2007 www.ti.com copyright ?2001-2007, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. d a c 7 7 4 1 buffer +10v reference control logic input register i/o buffer dac register dac refen cs r/w rstsel data i/o v dd v ref v ss v cc refadj ref out ref in r offset rfb2 rfb1 sj v out agnd dgnd ldac rst 16 description the dac7741 is a 16-bit digital-to-analog converter (dac) which provides 16 bits of monotonic performance over the specified operating temperature range and offers a +10v, low-drift internal reference. designed for automatic test equip- ment and industrial process control applications, the dac7741 output swing can be configured in a 10v, 5v, or +10v range. the flexibility of the output configuration allows the dac7741 to provide both unipolar and bipolar operation by pin strapping. the dac7741 includes a high-speed output amplifier with a maximum settling time of 5 s to 0.003% fsr for a 20v full-scale change and only consumes 100mw (typical) of power. the dac7741 features a standard 16-bit parallel interface with double buffering to allow asynchronous updates of the analog output and data read-back to support data integrity verification prior to an update. a user-programmable reset control allows the dac output to reset to min-scale (0000 h ) or mid-scale (8000 h ) overriding the dac register values. the dac7741 is available in a lqfp-48 package and four performance grades specified to operate from 0 c to +70 c and 40 c to +85 c. features low power: 150mw maximum +10v internal reference unipolar or bipolar operation settling time: 5 s to 0.003% fsr 16-bit monotonicity, C40 c to +85 c 10v, 5v or +10v configurable voltage output reset to min-scale or mid-scale double-buffered data input input register data readback small lqfp-48 package applications process control ate pin electronics closed-loop servo control motor control data acquisition systems production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. all trademarks are the property of their respective owners.
dac7741 2 sbas248b www.ti.com electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. absolute maximum ratings (1) v cc to v ss ........................................................................... 0.3v to +34v v cc to agnd ...................................................................... 0.3v to +17v v ss to agnd ...................................................................... 17v to +0.3v agnd to dgnd ................................................................. 0.3v to +0.3v ref in to agnd ............................................................. 0v to v cc 1.4v v dd to dgnd ........................................................................ 0.3v to +6v digital input voltage to dgnd ................................. 0.3v to v dd + 0.3v digital output voltage to dgnd .............................. 0.3v to v dd + 0.3v operating temperature range ........................................ 40 c to +85 c storage temperature range ......................................... 65 c to +150 c junction temperature .................................................................... +150 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. package/ordering information linearity differential specified error nonlinearity package temperature ordering package transport product (lsb) (lsb) package-lead designator (1) range number marking media, quantity dac7741y 6 4 lqfp-48 pt 40 c to +85 c dac7741y/250 dac7741y tape and reel, 250 """""" dac7741y/2k " tape and reel, 2000 dac7741yb 4 2 lqfp-48 pt 40 c to +85 c dac7741yb/250 dac7741yb tape and reel, 250 """""" dac7741yb/2k " tape and reel, 2000 dac7741yc 3 1 lqfp-48 pt 40 c to +85 c dac7741yc/250 dac7741yc tape and reel, 250 """""" dac7741yc/2k " tape and reel, 2000 dac7741yl 2 1 lqfp-48 pt 0 c to +70 c dac7741yl/250 dac7741yl tape and reel, 250 """""" dac7741yl/2k " tape and reel, 2000 note: (1) for the most current package and ordering information, see the package option addendum at the end of this document, o r see the ti web site at www.ti.com. dac7741y dac7741yb parameter conditions min typ max min typ max units accuracy linearity error (inl) 6 4 lsb t a = 25 c 5 3 lsb differential linearity error (dnl) 4 2 lsb monotonicity 14 15 bits offset error 0.1 ? % of fsr offset error drift 2 ? ppm/ c gain error with internal ref 0.4 0.25 % of fsr with external ref 0.25 0.1 % of fsr gain error drift with internal ref 15 10 ppm/ c psrr (v cc or v ss ) at full-scale 50 200 ?? ppm/v analog output (1) voltage output (2) +11.4/ 4.75 (1) 0 to 10 ? v +11.4/ 11.4 (1) 10 ? v +11.4/ 6.4 (1) 5 ? v output current 5 ? ma output impedance 0.1 ? ? maximum load capacitance 200 ? pf short-circuit current 15 ? ma short-circuit duration agnd indefinite ? reference reference output 9.96 10 10.04 9.975 ? 10.025 v ref out impedance 400 ? ? ref out voltage drift 15 10 ppm/ c ref out voltage adjustment (3) 25 ? mv ref in input range (4) 4.75 v cc 1.4 ?? v ref in input current 10 ? na refadj input range absolute max value that 010 ?? v can be applied is v cc refadj input impedance 50 ? k ? v ref output current 2+2 ?? ma v ref impedance 1 ? ? electrical characteristics all specifications at t a = t min to t max , v cc = +15v, v ss = 15v, v dd = +5v, internal reference enabled, unless otherwise noted.
dac7741 3 sbas248b www.ti.com dynamic performance settling time to 0.003% 20v output step 3 5 ?? s r l = 5k ? , c l = 200pf, with external ref out to ref in filter (5) digital feedthrough 2 ? nv-s output noise voltage at 10khz 100 ? nv/ hz digital input v ih |i h | < 10 a 0.7 v dd ? v v il |i l | < 10 a 0.3 v dd ? v digital output v oh i oh = 0.8ma 3.6 ? v v ol i ol = 1.6ma 0.4 ? v power supply v dd +4.75 +5.0 +5.25 ??? v v cc +11.4 +15.75 ?? v v ss bipolar operation 15.75 11.4 ?? v unipolar operation 15.75 4.75 ?? v i dd 100 ? a i cc unloaded 4 6 ?? ma i ss unloaded 4 2.5 ?? ma power no load, ext. reference 85 ? mw no load, int. reference 100 150 ?? mw temperature range specified performance 40 +85 ?? c ? specifications same as grade to the left. notes: (1) with minimum v cc /v ss requirements, internal reference enabled. (2) please refer to the theory of operation section for more information with respect to output voltage configurations. (3) see figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) the minimum value for ref in must be equal to the greater of v ss +14v and +4.75v, where +4.75v is the minimum voltage allowed. (5) reference low-pass filter values: 100k ? , 1.0 f (see figure 10). electrical characteristics (cont.) all specifications at t a = t min to t max , v cc = +15v, v ss = 15v, v dd = +5v, internal reference enabled, unless otherwise noted. dac7741y dac7741yb parameter conditions min typ max min typ max units
dac7741 4 sbas248b www.ti.com dac7741yl dac7741yc parameter conditions min typ max min typ max units accuracy linearity error (inl) 2 3lsb t a = 25 c 1 2lsb differential linearity error (dnl) 1 1lsb monotonicity 16 16 bits offset error 0.1 ? % of fsr offset error drift 2 ? ppm/ c gain error with internal ref 0.4 0.2 % of fsr with external ref 0.25 0.1 % of fsr gain error drift with internal ref 15 7 ppm/ c psrr (v cc or v ss ) at full-scale 50 200 ?? ppm/v analog output (1) voltage output (2) +11.4/ 4.75 (1) 0 to 10 ? v +11.4/ 11.4 (1) 10 ? v +11.4/ 6.4 (1) 5 ? v output current 5 ? ma output impedance 0.1 ? ? maximum load capacitance 200 ? pf short-circuit current 15 ? ma short-circuit duration agnd indefinite ? reference reference output 9.96 10 10.04 9.975 ? 10.025 v ref out impedance 400 ? ? ref out voltage drift 15 7 ppm/ c ref out voltage adjustment (3) 25 ? mv ref in input range (4) 4.75 v cc 1.4 ?? v ref in input current 10 ? na refadj input range absolute max value that 010 ?? v can be applied is v cc refadj input impedance 50 ? k ? v ref output current 2+2 ?? ma v ref impedance 1 ? ? dynamic performance settling time to 0.003% 20v output step 3 5 ?? s r l = 5k ? , c l = 200pf, with external ref out to ref in filter (5) digital feedthrough 2 ? nv-s output noise voltage at 10khz 100 ? nv/ hz digital input v ih |i h | < 10 a 0.7 v dd ? v v il |i l | < 10 a 0.3 v dd ? v digital output v oh i oh = 0.8ma 3.6 ? v v ol i ol = 1.6ma 0.4 ? v power supply v dd +4.00 +5.0 +5.25 +4.75 ?? v v cc +11.4 +15.75 ?? v v ss bipolar operation 15.75 11.4 ?? v unipolar operation 15.75 4.75 ?? v i dd 100 ? a i cc unloaded 4 6 ?? ma i ss unloaded 4 2.5 ?? ma power no load, ext. reference 85 ? mw no load, int. reference 100 150 ?? mw temperature range specified performance 0 70 40 +85 c ? specifications same as grade to the left. notes: (1) with minimum v cc /v ss requirements, internal reference enabled. (2) please refer to the theory of operation section for more information with respect to output voltage configurations. (3) see figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) the minimum value for ref in must be equal to the greater of v ss +14v and +4.75v, where +4.75v is the minimum voltage allowed. (5) reference low-pass filter values: 100k ? , 1.0 f (see figure 10). electrical characteristics all specifications at t a = t min to t max , v cc = +15v, v ss = 15v, v dd = +5v, internal reference enabled, unless otherwise noted.
dac7741 5 sbas248b www.ti.com top view lqfp pin configuration pin name description 1 nc no connection 2v ss negative analog power supply. 3v cc positive analog power supply. 4v ref buffered output from ref in , can be used to drive external devices. internally, this pin directly drives the dac circuitry. 5r offset offsetting resistor 6 agnd analog ground (must be tied to analog ground) 7 agnd analog ground (must be tied to analog ground) 8 rfb2 feedback resistor 2, used to configure dac output range. 9 rfb1 feedback resistor 1, used to configure dac output range. 10 sj summing junction of the output amplifier 11 v out dac voltage output 12 nc no connection 13 nc no connection 14 nc no connection 15 nc no connection 16 db0 data bit 0 (lsb) 17 db1 data bit 1 18 db2 data bit 2 19 db3 data bit 3 20 db4 data bit 4 21 db5 data bit 5 22 db6 data bit 6 23 nc no connection 24 nc no connection 25 nc no connection 26 test reserved, connect to dgnd 27 db7 data bit 7 pin descriptions 36 35 34 33 32 31 30 29 28 27 26 25 nc db15 db14 db13 db12 db11 db10 db9 db8 db7 test nc nc ref in refadj ref out refen rstsel r/w cs ldac rst v dd dgnd nc nc nc db0 db1 db2 db3 db4 db5 db6 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 nc v ss v cc v ref r offset agnd agnd rfb2 rfb1 sj v out nc 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 dac7741 28 db8 data bit 8 29 db9 data bit 9 30 db10 data bit 10 31 db11 data bit 11 32 db12 data bit 12 33 db13 data bit 13 34 db14 data bit 14 35 db15 data bit 15 (msb) 36 nc no connection 37 dgnd digital ground 38 v dd digital power supply 39 rst v out reset; active low, depending on the state of rstsel, the dac register is either reset to mid- scale or min-scale. 40 ldac dac register load control, rising edge triggered. data is loaded from the input register to the dac register. 41 cs chip select, active low 42 r/w enabled by cs, controls data read (high) and write (low) from or to the input register. 43 rstsel reset select; determines the action of rst. if high, rst will reset the dac register to mid- scale. if low, rst will reset the dac register to min-scale. 44 refen enables internal +10v reference (ref out ), active low. 45 ref out internal reference output 46 refadj internal reference trim. (acts as a gain adjustment input when the internal reference is used.) 47 ref in reference input 48 nc no connection pin name description
dac7741 6 sbas248b www.ti.com parameter description min typ max units t rcs cs low for read 100 ns t rds r/w high to cs low 10 ns t rdh r/w high after cs high 10 ns t dz cs high to data bus high impedance 10 70 ns t csd cs low to data bus valid 85 100 ns t wcs cs low for write 30 ns t ws r/w low to cs low 10 ns t wh r/w low after cs high 10 ns t ls cs low to ldac high 40 ns t lh cs low after ldac high 0 ns t lx ldac high 30 ns t ds data valid to cs low 0 ns t dh data valid after cs high 20 ns t lwd ldac low 40 ns t ss rstsel valid before rst low 0 ns t sh rstsel valid after rst high 10 ns t rss rst low 30 ns t s voltage output settling time 5 s timing characteristics dac7741y timing diagrams reset timing data in db15-db0 t ds t ls t lh t s t lx t wh t lwd t dh t ws t wcs data valid cs r/w ldac v out 0.003% of fsr error bands t rcs t rds t rdh t csd t dz data valid data out db15-db0 r/w cs rstsel (rstsel = low) (rstsel = high) rst v out v out t ss t sh t rss t s +fs +fs fs fs min-scale mid-scale write cycle read cycle
dac7741 7 sbas248b www.ti.com typical characteristics t a = +25 c (unless otherwise noted) 6 4 2 0 2 4 6 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 inl (lsb) dnl (lsb) linearity error and differential linearity error vs digital input code 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h bipolar configuration: v out = 10v to +10v t a = 85 c, internal reference enabled 6 4 2 0 2 4 6 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 inl (lsb) dnl (lsb) linearity error and differential linearity error vs digital input code 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h bipolar configuration: v out = 10v to +10v t a = 25 c, internal reference enabled 6 4 2 0 2 4 6 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 inl (lsb) dnl (lsb) linearity error and differential linearity error vs digital input code 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h bipolar configuration: v out = 10v to +10v t a = 40 c, internal reference enabled 0.125 0.100 0.075 0.050 0.025 0.000 0.025 error (%) 40 15 10 35 60 85 temperature ( c) gain error vs temperature int. ref, unipolar mode: v out = 0 to +10v int. ref, bipolar mode: v out = 10 to +10v ext. ref, unipolar mode: v out = 0 to +10v ext. ref, bipolar mode: v out = 10 to +10v 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 i cc (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h v cc supply current vs digital input code bipolar configuration: v out = 10v to +10v internal reference enabled, t a = 25 c 5 4 3 2 1 0 1 2 3 4 5 error (mv) offset error vs temperature 40 15 10 35 60 85 temperature ( c) v out = 10 to +10v v out = 0 to +10v
dac7741 8 sbas248b www.ti.com typical characteristics (cont.) t a = +25 c (unless otherwise noted) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 i cc (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h v cc supply current vs digital input code bipolar configuration: v out = 10v to +10v external reference, refen = 5v, t a = 25 c 1.50 1.75 2.00 2.25 2.50 2.75 i ss (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h v ss supply current vs digital input code bipolar configuration: v out = 10v to +10v t a = 25 c supply current vs temperature load current excluded, v cc = +15v, v ss = 15v bipolar v out configuration: 10v to +10v i cc i ss 6 5 4 3 2 1 0 1 2 3 4 i cc , i ss (ma) 40 15 10 35 60 85 temperature ( c) 1000 800 600 400 200 0 i dd ( a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v logic (v) supply current vs logic input voltage t a = 25 c, transition shown for one data input (cs = 5v, r/w = 0) 100 90 80 70 60 50 40 30 20 10 0 frequency histogram of v cc current consumption 3.000 3.500 4.000 4.500 5.000 i cc (ma) bipolar output configuration internal reference enabled code = 5555 h 100 90 80 70 60 50 40 30 20 10 0 frequency histogram of v ss current consumption 3.50 3.00 2.50 2.00 1.50 i ss (ma) bipolar output configuration internal reference enabled code = 5555 h
dac7741 9 sbas248b www.ti.com typical characteristics (cont.) t a = +25 c (unless otherwise noted) 10 0 10 20 30 40 50 60 70 80 psrr (db) 0.1k 1k 10k 100k 1m 10m frequency (hz) bipolar configuration: 10v v out code 8000 h v ss , v cc = 15v + 1vp-p v dd = 5v + 0.5vp-p v ss v cc v dd power suppy rejection ratio vs frequency (measured at v out ) 10 0 10 20 30 40 50 60 70 80 psrr (db) 0.01k 0.1k 1k 10k 100k 1m 10m power suppy rejection ratio vs frequency (measured at v out ) frequency (hz) v ss v cc v dd bipolar configuration: 10v v out , code ffff h v ss , v cc = 15v + 1vp-p, v dd = 5v + 0.5vp-p internal reference start-up v cc (5v/div) ref out (2v/div) time (2ms/div) 0v 15v 0v 10v 10.015 10.010 10.005 10.000 9.995 9.990 9.985 ref out (v) 40 15 10 35 60 85 temperature ( c) internal reference output vs temperature loaded to v cc v cc = +15v loaded to agnd 11.0 10.5 10.0 9.5 9.0 8.5 ref out (v) ref out load(k ? ) ref out voltage vs load 1 10 100 1k source sink output voltage vs r load 12 8 4 0 4 8 12 v out (v) 0.0 0.1 1.0 10.0 100.0 r load (k ?)
dac7741 10 sbas248b www.ti.com typical characteristics (cont.) t a = +25 c (unless otherwise noted) 900 800 700 600 500 400 300 200 100 0 output noise (nv/hz) 0.01k 0.1k 1k 10k 100k 1m 10m output noise vs frequency frequency (hz) unipolar configuration, internal reference enabled code ffff h code 0000 h 800 700 600 500 400 300 200 100 0 output noise (nv/ hz) 0.01k 0.1k 1k 10k 100k 1m 10m output noise vs frequency frequency (hz) bipolar configuration: 10v, internal reference enabled code 0000 h code ffff h code 8000 h broadband noise v out (v, 50 v/div) time (100 s/div) internal reference enabled filtered with 1.6hz low-pass code ffff h , bipolar 10v configuration 10khz measurement bw unipolar full-scale settling time time (2 s/div) unipolar configuration: v out = 0v to +10v zero-scale to + full-scale change 5k ?, 200pf load large-signal output (5v/div) small-signal error (300 v/div) bipolar full-scale settling time time (2 s/div) bipolar configuration: v out = 10v to +10v full-scale to + full-scale change 5k ?, 200pf load large-signal output (5v/div) small-signal error (300 v/div) 10 0 10 20 30 40 50 60 70 80 psrr (db) 1 10 100 1k 10k 100k 1m 10m power-suppy rejection ratio vs frequency (measured at ref out ) frequency (hz) v ss v cc v dd internal reference enabled v ss , v cc = 15v + 1vp-p, v dd = 5v + 0.5vp-p
dac7741 11 sbas248b www.ti.com typical characteristics (cont.) t a = +25 c (unless otherwise noted) bipolar configuration: v out = 10 to +10v +full-scale to full-scale 5k ? , 200pf load large-signal output (5v/div) bipolar full-scale settling time time (2 s/div) small-signal error (300 v/div) code 8000 h to 7fff h bipolar configuration: 10v v out mid-scale glitch time (1 s/div) v out (v, 200mv/div) mid-scale glitch time (1 s/div) v out (v, 200mv/div) code 7fff h to 8000 h bipolar configuration: 10v v out digital feedthrough time (200ns/div) v out = 8000 h (100mv/div) all data bits toggling (5v/div) cs = 5v unipolar configuration: v out = 0v to +10v +full-scale to zero-scale change 5k ? , 200pf load large-signal output (5v/div) unipolar full-scale settling time time (2 s/div) small-signal error (150 v/div)
dac7741 12 sbas248b www.ti.com theory of operation the dac7741 is a voltage output, 16-bit dac with a +10v built-in internal reference. the architecture is an r-2r ladder configuration with the three msbs segmented, followed by an operational amplifier that serves as a buffer. the output buffer is designed to allow user-configurable output adjust- ments, giving the dac7741 output voltage ranges of 0v to +10v, 5v to +5v, or 10v to +10v. please refer to figures 2, 3, and 4 for pin configuration information. the digital input is a parallel word made up of the 16-bit dac code, which is then loaded into the dac register using the ldac input pin. the converter can be powered from 12v to 15v dual analog supplies and a +5v logic supply. the device offers a reset function, which immediately sets the dac output voltage and dac register to min-scale (code 0000 h ) or mid-scale (code 8000 h ). the data i/o and reset functions are discussed in more detail in the following sec- tions. figure 1. dac7741 architecture. figure 2. basic operation: v out = 0 to +10v. 2r 2r 2r 2r 2r 2r 2r 2r 2r r/4 r/2 r/2 r/4 r/4 r r offset rfb2 rfb1 sj v out v ref v ref agnd ref in ref adj ref out +10v internal reference buffer 1 f 0.1 f v dd 1 f 0.1 f v ss 1 f 0.1 f v cc control bus data bus data bus 36 35 34 33 32 31 30 29 28 27 26 25 nc db15 db14 db13 db12 db11 db10 db9 db8 db7 test nc dgnd v dd rst ldac cs r/w rstsel refen ref out refadj ref in nc nc nc db6 db5 db4 db3 db2 db1 db0 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 nc v ss v cc v ref r offset agnd agnd rfb2 rfb1 sj v out nc 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 dac7741 (0v to +10v)
dac7741 13 sbas248b www.ti.com figure 3. basic operation: v out = 5v to +5v. figure 4. basic operation: v out = 10v to +10v. 1 f 0.1 f v dd 1 f 0.1 f v ss 1 f 0.1 f v cc control bus data bus data bus 36 35 34 33 32 31 30 29 28 27 26 25 nc db15 db14 db13 db12 db11 db10 db9 db8 db7 test nc 1 2 3 4 5 6 7 8 9 10 11 12 nc v ss v cc v ref r offset agnd agnd rfb2 rfb1 sj v out nc 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 dac7741 ( 5v to +5v) dgnd v dd rst ldac cs r/w rstsel refen ref out refadj ref in nc nc nc db6 db5 db4 db3 db2 db1 db0 nc nc nc 1 f 0.1 f v dd 1 f 0.1 f v ss 1 f 0.1 f v cc control bus data bus data bus 36 35 34 33 32 31 30 29 28 27 26 25 nc db15 db14 db13 db12 db11 db10 db9 db8 db7 test nc 1 2 3 4 5 6 7 8 9 10 11 12 nc v ss v cc v ref r offset agnd agnd rfb2 rfb1 sj v out nc 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 dac7741 ( 10v to +10v) dgnd v dd rst ldac cs r/w rstsel refen ref out refadj ref in nc nc nc db6 db5 db4 db3 db2 db1 db0 nc nc nc
dac7741 14 sbas248b www.ti.com analog outputs the output amplifier can swing to within 1.4v of the supply rails, specified over the 40 c to +85 c temperature range. this allows for a 10v dac voltage output operation from 12v supplies with a typical 5% tolerance. when the dac7741 is configured for a unipolar, 0v to 10v output, a negative voltage supply is required. this is due to internal biasing of the output stage. please refer to the electrical characteristics table for more information. the minimum and maximum voltage output values are de- pendent upon the output configuration implemented and reference voltage applied to the dac7741. please note that v ss (the negative power supply) must be in the range of 4.75v to 15.75v for unipolar operation. the voltage on v ss sets several bias points within the converter and is required in all modes of operation. if v ss is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured. supply sequence is important in establishing the correct startup of the dac. the digital supply (v dd ) needs to estab- lish correct bias conditions before the analog supplies (v cc , v ss ) are brought up. if the digital supply cannot be brought up first, it must come up before either analog supply (v cc or v ss ), with the preferred sequence of: v ss (device substrate), v dd then v cc . reference inputs the dac7741 provides a built-in +10v voltage reference and on-chip buffer to allow external component reference drive. to use the internal reference, refen must be low, enabling the reference circuitry of the dac7741 (see table i) and the ref out pin must be connected to ref in . this is the input to the on-chip reference buffer. the buffers output is provided at refen action 1 internal reference disabled; ref out = high impedance 0 internal reference enabled; ref out = +10v table i. refen action. table ii. dac7741 logic truth table. the v ref pin. in this configuration, v ref is used to setup the dac7741 output amplifier into one of three voltage output modes as discussed earlier. v ref can also be used to drive other system components requiring an external reference. the internal reference of the dac7741 can be disabled when use of an external reference is desired. when using an external reference, the reference input, ref in , can be any voltage between 4.75v (or v ss + 14v, whichever is greater) and v cc 1.4v. digital interface table iii shows the data format for the dac7741 and table ii illustrates the basic control logic of the device. the interface consists of a chip select input (cs), read/write control input (r/w), data inputs (db0-db15) and a load dac input (ldac). an asynchronous reset input (rst) which is active low, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (rstsel) signal. the dac code is provided via a 16-bit parallel interface, as shown in table ii. the input word makes up the dac code to be loaded into the data input register of the device. the data is latched into the input register on rising cs and is loaded into the dac register upon reception of a rising edge on the ldac input. this action updates the analog output, v out , to the desired value. ldac inputs of multiple dac7741 devices can be connected when a synchronized update of numerous dac outputs is desired. please refer to the timing section for more detailed data i/o information. control status command r/w cs rst rstsel ldac input register dac register mode l l h x h, l, write hold write data to input register xh h x hold write update dac register with data from input register. ll h x transparent write write dac register directly from data bus h l h x h, l, read hold read data in input register. x h h x h, l, hold hold no change xx l l x reset to min-scale reset to min-scale reset to input and dac register (0000 h ) min- scale xx l h x reset to mid-scale reset to mid-scale reset to input and dac register (8000 h ) mid-scale analog output table iii. dac7741 data format. digital input unipolar configuration bipolar configuration unipolar straight binary bipolar offset binary 0x0000 zero (0v) full-scale ( v ref or v ref /2) 0x0001 zero + 1lsb full-scale + 1lsb :: : 0x8000 1/2 full-scale bipolar zero 0x8001 1/2 full-scale + 1lsb bipolar zero + 1lsb :: : 0xffff full-scale (v ref 1lsb) +full-scale (+v ref 1lsb or +v ref /2 1lsb)
dac7741 15 sbas248b www.ti.com dac reset the rst and rstsel inputs control the reset of the analog output. the reset command is level triggered by a low signal on rst. once rst is low, the dac output will begin settling to the mid-scale or min-scale code depending on the state of the rstsel input. a high value on rstsel will cause v out to reset to the mid-scale code (8000h) and a low value will reset v out to min-scale (0000 h ). a change in the state of the rstsel input while rst is low will cause a corresponding change in the reset command selected internally and conse- quently change the output value of v out of the dac. note that a valid reset signal also resets the input register of the dac to the value specified by the state of rstsel. gain and offset calibration the architecture of the dac7741 is designed in such a way as to allow for easily configurable offset and gain calibration using a minimum of external components. the dac7741 has built-in feedback resistors and output amplifier summing points brought out of the package in order to make the absolute calibration possible. figures 5 and 6 illustrate the relationship of offset and gain adjustments for the dac7741 in a unipolar configuration and in a bipolar configuration, respectively. when calibrating the dac output, offset should be adjusted first to avoid first order interaction of adjustments. in unipolar mode, the dac7741 offset is adjusted from code 0000 h and for either bipolar mode, offset adjustments are made at code 8000 h . gain adjustment can then be made at code ffff h for each configuration, where the output of the dac should be at +10v for the 0v to +10v 1lsb or 10v output range and +5v 1lsb for the 5v output range. figure 7 shows the generalized external offset and gain adjustment circuitry using potentiometers. digital input h input = ffff h input = 0000 gain adjust rotates the line 1lsb + full scale full scale range analog output (+v ref ) zero scale (agnd) offset adjust translates the line digital input input = 0000 h gain adjust rotates the line 1lsb full scale range + full scale full-scale ( v ref or v ref /2) offset adjust translates the line h input = ffff input = 8000 h analog output (+v ref or +v ref /2) figure 5. relationship of offset and gain adjustments for v out = 0v to +10v output configuration. figure 6. relationship of offset and gain adjustments for v out = 10v to +10v output configuration. (same theory applies for v out = 5v to +5v). figure 7. generalized external calibration circuitry for gain and symmetrical offset adjustment. nc v ss v cc v ref r offset agnd agnd rfb2 rfb1 sj v out 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 optional gain adjust (other connections omitted for clarity) ref out refadj ref in nc optional offset adjust r pot1 r s v oadj + i sj r 1 r pot2
dac7741 16 sbas248b www.ti.com figure 8. offset adjustment transfer characteristic. offset adjustment offset adjustment is accomplished by introducing a small current into the summing junction (sj) of the dac7741. the voltage at sj, or v sj , is dependent on the output configura- tion of the dac7741. see table iv for the required pin strapping for a given configuration and the nominal values of v sj for each output range. reference output pin strapping v sj (1) configuration configuration r offset rfb1 rfb2 internal 0v to +10v to v ref to v out to v out +5v reference 10v to +10v nc nc to v out +3.333v 5v to +5v to agnd to v out to v out +1.666v external 0v to v ref to v ref to v out to v out v ref /2 reference v ref to v ref nc nc to v out v ref /3 v ref /2 to v ref /2 to agnd to v out to v out v ref /6 note: (1) voltage measured at v sj for a given configuration. table iv. nominal v sj vs. v out and reference configuration. output r pot2 r 1 r s i sj nominal configuration range offset adjustment 0v to +10v 10k 0 2.5m 2 a 25mv 10v to +10v 10k 5k 1.5m 2.2 a 55mv 5v to +5v 10k 20k 1m 1.7 a 21mv table v. recommended external component values for symmetrical offset adjustment (v ref = 10v). the current level required to adjust the dac7741 offset can be created by using a potentiometer divider as shown in figure 7. another alternative is to use a unipolar dac in order to apply a voltage, v oadj , to the resistor r s . a 2ua current range applied to sj will ensure offset adjustment coverage of the 0.1% maximum offset specification of the dac7741. when in a unipolar configuration (v sj = 5v), only a single resistor, r s , is needed for symmetrical offset adjustment with a 0v to 10v v oadj range. when in one of the two bipolar configurations, v sj is either +3.333v ( 10v range) or +1.666v ( 5v range), and circuit values chosen to match those given in table v will provide symmetrical offset adjust. please refer to figure 7 for component configuration. offset adjust range 10v to +10v v out configuration min (75% of typ) min (75% of typ) typ typ 50 25 0 25 50 offset adjustment at v out (mv) 22 0 11 i sj ( a) 0v to 10v and 5v to +5v v out configuration figure 8 illustrates the typical and minimum offset adjustment ranges provided by forcing a current at sj for a given output voltage configuration. gain adjustment when using the internal reference of the dac7741, gain adjustment is performed by adjusting the internal refer- ence voltage via the reference adjust pin, refadj. the effect of a reference voltage change on the gain of the dac output can be seen in the generic equation (for unipolar configuration): v out = v refin (n/65536) where n is represented in decimal format and ranges from 0 to 65535. refadj can be driven by a low impedance voltage source such as a unipolar, 0v to +10v dac or a potentiometer (less than 100k ? ) as shown in figure 7. since the input imped- ance of refadj is typically 50k ? , the smaller the resistance of the potentiometer, the more linear the adjustment will be. a 10k ? potentiometer is suggested if linearity of the refer- ence adjustment is of concern. ref out adjust range 40 30 20 10 0 10 20 30 40 ref out adjustment (mv) 0246810 refadj (v) typical ref out adjustment range minimum ref out adjustment range figure 9. internal reference adjustment transfer charac- teristic. voltage at refadj ref out voltage refadj = 0v 10v + 25mv (min) refadj = 5v or nc (1) 10v refadj = 10v 10v 25mv (max) note: "nc" is "not connected" table vi. minimum internal reference adjustment range. when the dac7741 internal reference is not used, gain adjustments can be made via trimming the external refer- ence applied to the dac at ref in . this can be accomplished through using a potentiometer, unipolar dac, or other means of precision voltage adjustment to control the voltage pre- sented to the dac7741 by the external reference. figure 9 and table vi summarize the range of adjustment of the internal reference via refadj.
dac7741 17 sbas248b www.ti.com layout a precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. the dac7741 offers separate digital and analog supplies, as it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switching speed, the more important it will become to separate the analog and digital ground and supply planes at the device. since the dac7741 has both analog and digital ground pins, return currents can be better controlled and have less effect on the dac output error. ideally, agnd would be connected directly to an analog ground plane and dgnd to the digital ground plane. the analog ground plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. the voltages applied to v cc and v ss should be well regulated and low noise. switching power supplies and dc/dc convert- ers will often have high-frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high-frequency spikes as their internal logic switches states. this noise can easily couple into the dac output voltage through various paths between the power connec- tions and analog output. in addition, a 1 f to 10 f bypass capacitor in parallel with a 0.1 f bypass capacitor is strongly recommended for each supply input. in some situations, additional bypassing may be required, such as a 100 f electrolytic capacitor or even a "pi" filter made up of inductors and capacitors all designed to essentially low-pass filter the analog supplies, removing any high frequency noise components. noise performance increased noise performance of the dac output can be achieved by filtering the voltage reference input to the dac7741. figure 10 shows a typical internal reference filter schematic. a low-pass filter applied between the ref out and ref in pins can increase noise immunity at the dac and output amplifier. the ref out pin can source a maximum of 50 a so care should be taken in order to avoid overloading the internal reference output . nc v ss v cc 1 2 3 43 44 45 46 47 48 (other connections omitted for clarity) rstsel refen ref out refadj ref in nc 100k ? 1 f figure 10. internal reference filter.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) dac7741y/250 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741y/2k active lqfp pt 48 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yb/250 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yb/250g4 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yc/250 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yc/250g4 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yc/2k active lqfp pt 48 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yl/250 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yl/250g4 active lqfp pt 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yl/2k active lqfp pt 48 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr dac7741yl/2kg4 active lqfp pt 48 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti package option addendum www.ti.com 16-apr-2009 addendum-page 1
to customer on an annual basis. package option addendum www.ti.com 16-apr-2009 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant dac7741y/250 lqfp pt 48 250 177.8 16.4 9.6 9.6 1.9 12.0 16.0 q2 dac7741y/2k lqfp pt 48 2000 330.0 16.8 9.6 9.6 1.9 12.0 16.0 q2 dac7741yb/250 lqfp pt 48 250 177.8 16.4 9.6 9.6 1.9 12.0 16.0 q2 dac7741yc/250 lqfp pt 48 250 177.8 16.4 9.6 9.6 1.9 12.0 16.0 q2 dac7741yc/2k lqfp pt 48 2000 330.0 16.8 9.6 9.6 1.9 12.0 16.0 q2 dac7741yl/250 lqfp pt 48 250 177.8 16.4 9.6 9.6 1.9 12.0 16.0 q2 dac7741yl/2k lqfp pt 48 2000 330.0 16.8 9.6 9.6 1.9 12.0 16.0 q2 package materials information www.ti.com 20-dec-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) dac7741y/250 lqfp pt 48 250 190.5 212.7 31.8 dac7741y/2k lqfp pt 48 2000 346.0 346.0 33.0 dac7741yb/250 lqfp pt 48 250 190.5 212.7 31.8 dac7741yc/250 lqfp pt 48 250 190.5 212.7 31.8 dac7741yc/2k lqfp pt 48 2000 346.0 346.0 33.0 dac7741yl/250 lqfp pt 48 250 190.5 212.7 31.8 dac7741yl/2k lqfp pt 48 2000 346.0 346.0 33.0 package materials information www.ti.com 20-dec-2008 pack materials-page 2
mechanical data mtqf003a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pt (s-pqfp-g48) plastic quad flatpack 4040052 / c 11/96 0,13 nom 0,17 0,27 25 24 sq 12 13 36 37 6,80 7,20 1 48 5,50 typ 0,25 0,45 0,75 0,05 min sq 9,20 8,80 1,35 1,45 1,60 max gage plane seating plane 0,10 0 7 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. this may also be a thermally enhanced plastic package with leads conected to the die pads.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dlp? 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